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publication number s29al016d_00 revision a amendment 7 issue date november 27, 2007 s29al016d s29al016d cover sheet 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s29al016d s29al016d_00_a7 november 27, 2007 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
publication number s29al016d_00 revision a amendment 7 issue date november 27, 2007 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ? manufactured on 200 nm process technology ? fully compatible with 200 nm am29lv160d and mbm29lv160e devices ? flexible sector architecture ? one 16 kbyte, two 8 kbyte, one 32 kbyte, and thirty-one 64 kbyte sectors (byte mode) ? one 8 kword, two 4 kword, one 16 kword, and thirty-one 32 kword sectors (word mode) ? sector protection features ? a hardware method of locking a sector to prevent any program or erase operations within that sector ? sectors can be locked in-system or via programming equipment ? temporary sector unprotect feature allows code changes in previously locked sectors ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? top or bottom boot block configurations available ? compatibility with jedec standards ? pinout and software compatible with single-power supply flash ? superior inadvertent write protection performance characteristics ? high performance ? access times as fast as 70 ns ? extended temperature range (-40c to +125c) ? ultra low power consumption (typical values at 5 mhz) ? 200 na automatic sleep mode current ? 200 na standby mode current ? 9 ma read current ? 20 ma program/erase current ? cycling endurance: 1,000,000 cycles per sector typical ? data retention: 20 years typical package options ? 48-ball fbga ? 48-pin tsop ? 44-pin sop software features ? cfi (common flash interface) compliant ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices ? erase suspend/erase resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting program or erase operation completion hardware features ? ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method to reset the device to reading array data s29al016d 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 3.0 volt-only boot sector flash memory data sheet
4 s29al016d s29al016d_00_a7 november 27, 2007 data sheet general description the s29al016d is a 16 mbit, 3.0 volt -only flash memory organized as 2, 097,152 bytes or 1,048,576 words. the device is offered in 48-ball fbga, and 48-pin tsop packages. the word-wide data (x16) appears on dq15?dq0; the byte-wide (x8) data appears on dq7?dq0. this device is designed to be programmed in- system with the standard system 3.0 volt v cc supply. a 12.0 v v pp or 5.0 v cc are not required for write or erase operations. the device can also be programmed in standard eprom programmers. the device offers access times of 70 ns and 90 ns allowing high speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provi ded for the program and erase operations. the s29al016d is entirely comm and set compatible with the jedec single-power-supply flash standard . commands are written to the command register usin g standard microprocessor write timings. register contents serve as input to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data n eeded for the programming and erase operations. reading data out of the device is similar to re ading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithm?an internal algorithm that automati cally times the program pulse widths and verifies proper cell margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program dat a instead of four. device erasure occurs by executing the er ase command sequence. this initiates the embedded erase algorithm?an internal algorithm that automatically prepr ograms the array (if it is not already programmed) before executing the erase op eration. during erase, the device au tomatically times the erase pulse widths and verifies proper cell margin. the host system can detect wh ether a program or erase operation is co mplete by observing the ry/by# pin, or by reading the dq7 (dat a# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of t he sectors of memory. this can be ac hieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to , any sector that is not selected fo r erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitr y. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when add resses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. spansion?s flash technology combines years of flas h memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection.
november 27, 2007 s29al016d_00_a7 s29al016d 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 special handling instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4. pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1 s29al016d standard products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7. device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 word/byte configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 requirements for reading array data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 writing commands/command sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 program and erase operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.6 automatic sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 reset#: hardware reset pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 7.8 output disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 autoselect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10 sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8. common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 hardware data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 reading array data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 autoselect command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.4 word/byte program command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.5 unlock bypass command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.6 chip erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.7 sector erase command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.8 erase suspend/erase resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10. command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11. write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.2 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.3 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.4 dq2: toggle bit ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.5 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.6 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.7 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13. operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 14. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 14.2 zero power flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 16. key to switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 17. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 17.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 17.2 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17.3 word/byte configuration (byte#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 17.4 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 17.5 temporary sector unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 17.6 alternate ce# controlled erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 18. erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 19. tsop, so, and bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 20. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.1 ts 048?48-pin standard tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.2 vbk048?48-ball fine-pitch ball grid array (fbga) 8.15 mm x 6.15 mm . . . . . . . . . . . . . . 51 20.3 so044?44-pin small outline package (sop) 28.20 mm x 13.30 mm. . . . . . . . . . . . . . . . . 52 21. revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.1 revision a (may 4, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.2 revision a1 (july 28, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.3 revision a2 (december 17, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 21.4 revision a3 (june 1, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 21.5 revision a4 (june 17, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21.6 revision a5 (may 22, 2006). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21.7 revision a6 (september 7, 2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 21.8 revision a7 (november 27, 2007). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
november 27, 2007 s29al016d_00_a7 s29al016d 7 data sheet figures figure 7.1 temporary sector unprotect operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7.2 in-system sector protect/unprotect algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9.1 program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9.2 erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 11.1 data# polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11.2 toggle bit algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13.1 maximum negative overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13.2 maximum positive overshoot waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 figure 14.1 i cc1 current vs. time (showing active and automatic s leep currents) . . . . . . . . . . . . . . . . 38 figure 14.2 typical i cc1 vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15.1 test setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16.1 input waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17.1 read operations timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17.2 reset# timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17.3 byte# timings for read operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17.4 byte# timings for write operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 17.5 program operation timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 17.6 chip/sector erase operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17.7 back to back read/write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 17.8 data# polling timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17.9 toggle bit timings (during embedded algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 17.10 dq2 vs. dq6 for erase and erase suspend operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.11 temporary sector unprotect/timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 17.12 sector protect/unprotect timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17.13 alternate ce# controlled write operation timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8 s29al016d s29al016d_00_a7 november 27, 2007 data sheet tables table 7.1 s29al016d device bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7.2 sector address tables (top boot device). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.3 sector address tables (bottom boot device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7.4 s29al016d autoselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8.1 cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8.2 system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8.4 primary vendor-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 table 10.1 s29al016d command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11.1 write operation status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15.1 test specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
november 27, 2007 s29al016d_00_a7 s29al016d 9 data sheet 1. product selector guide note see ac characteristics on page 40 for full specifications. 2. block diagram family part number s29al016d speed option voltage range: v cc = 2.7?3.6 v 70 90 max access time, ns (t acc ) 70 90 max ce# access time, ns (t ce ) 70 90 max oe# access time, ns (t oe ) 30 35 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# byte# ce# oe# stb stb dq0 ? dq15 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a0?a19
10 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 3. connection diagrams a1 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 nc we# reset# nc nc ry/by# a17 a7 a6 a5 a4 a3 a2 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 reset# a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce# v ss oe# dq0 dq8 dq1 dq9 dq2 dq10 dq3 dq11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 we# a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc standard sop
november 27, 2007 s29al016d_00_a7 s29al016d 11 data sheet 3.1 special handling instructions special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 nc a18 nc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 fb ga top view, balls facing down
12 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 4. pin configuration 5. logic symbol a0?a19 20 addresses dq0?dq14 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) byte# selects 8-bit or 16-bit mode ce# chip enable oe# output enable we# write enable reset# hardware reset pin ry/by# ready/busy output v cc 3.0 volt-only single power supply (see product selector guide on page 9 for speed options and voltage supply tolerances) v ss device ground nc pin not connected internally 20 16 or 8 dq0?dq15 (a-1) a0?a19 ce# oe# we# reset# byte# ry/by#
november 27, 2007 s29al016d_00_a7 s29al016d 13 data sheet 6. ordering information 6.1 s29al016d standard products spansion standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. notes 1. type 0 is standard. specify other options as required. 2. type 1 is standard. specify other options as required. 3. tsop and sop package markings omit packing type designator from ordering part number. 4. bga package marking omits leading s29 and packing type designator from ordering part number. valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29al016d 70 t a i 01 0 packing type 0=tray 1=tube 2 = 7? tape and reel 3 = 13? tape and reel model number 01 = v cc = 2.7 - 3.6v, top boot sector device 02 = v cc = 2.7 - 3.6v, bottom boot sector device temperature range i = industrial (-40c to +85c) n = extended (-40c to +125c) package material set a = standard f = pb-free package type t = thin small outline package (tsop) standard pinout b = fine-pitch ball-grid array package m = small outline package (sop) standard pinout speed option 70 = 70 ns access speed 90 = 90 ns access speed device number/description s29al016d 16 megabit flash memory manufactured using 200 nm process technology 3.0 volt-only read, program, and erase s29al016d valid combinations package description device number speed option package type, material, and temperature range model number packing type s29al016d 70, 90 tai, tfi, tan, tfn 01, 02 0, 3 (note 1) ts048 (note 3) tsop bai, bfi, ban, bfn 0, 2, 3 (note 1) vbk048 (note 4) fine-pitch bga mai, mfi, man, mfn 0, 1, 3 (note 2) so044 (note 3) sop
14 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 7. device bus operations this section describes the requiremen ts and use of the device bus operati ons, which are initiated through the internal command register. the command register itse lf does not occupy any add ressable memory location. the register is composed of latc hes that store the commands, along with the address and data information needed to execute the command. the cont ents of the register serve as inputs to the internal state machine. the state machine output s dictate the function of the device. table 7.1 lists the device bus operations, the inputs and control levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. legend l = logic low = v il h = logic high = v ih v id = 12.0 0.5 v x = don?t care a in = address in d in = data in d out = data out notes 1. addresses are a19:a0 in word mode (byte# = v ih ), a19:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see sector protection/ unprotection on page 19 . 7.1 word/byte configuration the byte# pin controls whether the device data i/o pins dq15?dq0 operate in the byte or word configuration. if the byte# pin is set at logic 1 , the device is in word configur ation, dq15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic 0 , the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/o pins dq8?dq14 are tri-stated , and the dq15 pin is used as an input for the lsb (a-1) address function. table 7.1 s29al016d device bus operations operation ce# oe# we# reset# addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h a in d out d out dq8?dq14 = high-z, dq15 = a-1 write l h l h a in d in d in standby v cc 0.3 v xx v cc 0.3 v x high-z high-z high-z output disable l h h h x high-z high-z high-z reset x x x l x high-z high-z high-z sector protect (note 2) lhl v id sector address, a6 = l, a1 = h, a0 = l d in xx sector unprotect (note 2) lhl v id sector address, a6 = h, a1 = h, a0 = l d in xx temporary sector unprotect xxx v id a in d in d in high-z
november 27, 2007 s29al016d_00_a7 s29al016d 15 data sheet 7.2 requirements for reading array data to read array data from the outputs, the syst em must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output cont rol and gates array data to the output pins. we# should remain at v ih . the byte# pin determines whether the de vice outputs array data in words or bytes. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory cont ent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the de vice remains enabled for read access until the command register contents are altered. see reading array data on page 25 for more information. refer to the ac read operations on page 40 for timing specifications and to figure 17.1 on page 40 for the timing diagram. i cc1 in dc characteristics on page 37 represents the active current specification for reading array data. 7.3 writing commands/command sequences to write a command or command sequence (which in cludes programming data to the device and erasing sectors of memory), the syste m must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin determines whet her the device accepts program data in bytes or words. see word/byte configuration on page 14 for more information. the device features an unlock bypass mode to facilitate faster programm ing. once the device enters the unlock bypass mode, only two writ e cycles are required to program a word or byte, instead of four. word/ byte program command sequence on page 26 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table 7.2 on page 17 and table 7.3 on page 18 indicate the address space that each sector occupies. a ?sector address? consists of the address bits required to uniquely select a sector. the command definitions on page 25 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autose lect command sequence, the device en ters the autoselect mode. the system can then read autoselec t codes from the internal register (whi ch is separate from the memory array) on dq7?dq0. standard read cycle timing s apply in this mode. refer to autoselect mode on page 19 and autoselect command sequence on page 25 for more information. i cc2 in dc characteristics on page 37 represents the active current specification for the write mode. ac characteristics on page 40 contains timing specification tables and timing diagrams for write operations. 7.4 program and erase operation status during an erase or program operatio n, the system may check the status of the operation by reading the status bits on dq7?dq0. standard read cycle timings and i cc read specifications apply. refer to write operation status on page 31 for more information, and to ac characteristics on page 40 for timing diagrams.
16 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 7.5 standby mode when the system is not reading or writing to the device , it can place the device in the standby mode. in this mode, current consumption is greatl y reduced, and the outputs are plac ed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when t he ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 and i cc4 represents the standby current spec ification shown in the table in dc characteristics on page 37 . 7.6 automatic sleep mode the automatic sleep mode minimizes flash device ener gy consumption. the devi ce automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals . standard address access timings pr ovide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics on page 37 represents the automatic sleep mode current specification. 7.7 reset#: hardware reset pin the reset# pin provides a hardware me thod of resetting the de vice to reading arra y data. when the system drives the reset# pin to v il for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset# pulse. the device also resets the internal state ma chine to reading array data. the operation that was interrupted should be reinitiated once the device is re ady to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system rese t would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or er ase operation, the ry /by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whet her the reset operation is complete. if reset# is asserted when a program or erase operat ion is not executing (ry/by# pin is 1 ), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset# pin returns to v ih . refer to the tables in ac characteristics on page 40 for reset# parameters and to figure 17.2 on page 41 for the timing diagram.
november 27, 2007 s29al016d_00_a7 s29al016d 17 data sheet 7.8 output disable mode when the oe# input is at v ih , output from the device is disabled. th e output pins are placed in the high impedance state. note address range is a19:a-1 in byte mode and a19:a0 in word mode. see word/byte configuration on page 14 . table 7.2 sector address tables (top boot device) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) byte mode (x8) word mode (x16) sa0 00000xxx 64/32 000 000?00ffff 00000?07fff sa1 00001xxx 64/32 010 000?01ffff 08000?0ffff sa2 00010xxx 64/32 020 000?02ffff 10000?17fff sa3 00011xxx 64/32 030 000?03ffff 18000?1ffff sa4 00100xxx 64/32 040 000?04ffff 20000?27fff sa5 00101xxx 64/32 050 000?05ffff 28000?2ffff sa6 00110xxx 64/32 060 000?06ffff 30000?37fff sa7 00111xxx 64/32 070 000?07ffff 38000?3ffff sa8 01000xxx 64/32 080 000?08ffff 40000?47fff sa9 01001xxx 64/32 090 000?09ffff 48000?4ffff sa1001010xxx 64/32 0a0 000?0affff 50000?57fff sa1101011xxx 64/32 0b0 000?0bffff 58000?5ffff sa1201100xxx 64/32 0c0 000?0cffff 60000?67fff sa1301101xxx 64/32 0d0 000?0dffff 68000?6ffff sa1401110xxx 64/32 0e0 000?0effff 70000?77fff sa1501111xxx 64/32 0f0 000?0fffff 78000?7ffff sa1610000xxx 64/32 100 000?10ffff 80000?87fff sa1710001xxx 64/32 110 000?11ffff 88000?8ffff sa1810010xxx 64/32 120 000?12ffff 90000?97fff sa1910011xxx 64/32 130 000?13ffff 98000?9ffff sa2010100xxx 64/32 140 000?14ffff a0000?a7fff sa2110101xxx 64/32 150 000?15ffff a8000?affff sa2210110xxx 64/32 160 000?16ffff b0000?b7fff sa2310111xxx 64/32 170 000?17ffff b8000?bffff sa2411000xxx 64/32 180 000?18ffff c0000?c7fff sa2511001xxx 64/32 190 000?19ffff c8000?cffff sa2611010xxx 64/32 1a0 000?1affff d0000?d7fff sa2711011xxx 64/32 1b0 000?1bffff d8000?dffff sa2811100xxx 64/32 1c0 000?1cffff e0000?e7fff sa2911101xxx 64/32 1d0 000?1dffff e8000?effff sa3011110xxx 64/32 1e0 000?1effff f0000?f7fff sa31111110xx 32/16 1f00 00?1f7fff f8000?fbfff sa3211111100 8/4 1f80 00?1f9fff fc000?fcfff sa3311111101 8/4 1fa00 0?1fbfff fd000?fdfff sa341111111x 16/8 1fc000?1 fffff fe000?fffff
18 s29al016d s29al016d_00_a7 november 27, 2007 data sheet note address range is a19:a-1 in byte mode and a19:a0 in word mode. see the word/byte configuration on page 14 . table 7.3 sector address tables (bottom boot device) sector a19 a18 a17 a16 a15 a14 a13 a12 sector size (kbytes/ kwords) address range (in hexadecimal) byte mode (x8) word mode (x16) sa0 0000000x 16/8 000000?003fff 00000?01fff sa1 00000010 8/4 004000?005fff 02000?02fff sa2 00000011 8/4 006000?007fff 03000?03fff sa3 000001xx 32/16 008 000?00ffff 04000?07fff sa4 00001xxx 64/32 010 000?01ffff 08000?0ffff sa5 00010xxx 64/32 020 000?02ffff 10000?17fff sa6 00011xxx 64/32 030 000?03ffff 18000?1ffff sa7 00100xxx 64/32 040 000?04ffff 20000?27fff sa8 00101xxx 64/32 050 000?05ffff 28000?2ffff sa9 00110xxx 64/32 060 000?06ffff 30000?37fff sa1000111xxx 64/32 070 000?07ffff 38000?3ffff sa1101000xxx 64/32 080 000?08ffff 40000?47fff sa1201001xxx 64/32 090 000?09ffff 48000?4ffff sa1301010xxx 64/32 0a0 000?0affff 50000?57fff sa1401011xxx 64/32 0b0 000?0bffff 58000?5ffff sa1501100xxx 64/32 0c0 000?0cffff 60000?67fff sa1601101xxx 64/32 0d0 000?0dffff 68000?6ffff sa1701110xxx 64/32 0e0 000?0effff 70000?77fff sa1801111xxx 64/32 0f0 000?0fffff 78000?7ffff sa1910000xxx 64/32 100 000?10ffff 80000?87fff sa2010001xxx 64/32 110 000?11ffff 88000?8ffff sa2110010xxx 64/32 120 000?12ffff 90000?97fff sa2210011xxx 64/32 130 000?13ffff 98000?9ffff sa2310100xxx 64/32 140 000?14ffff a0000?a7fff sa2410101xxx 64/32 150 000?15ffff a8000?affff sa2510110xxx 64/32 160 000?16ffff b0000?b7fff sa2610111xxx 64/32 170 000?17ffff b8000?bffff sa2711000xxx 64/32 180 000?18ffff c0000?c7fff sa2811001xxx 64/32 190 000?19ffff c8000?cffff sa2911010xxx 64/32 1a0 000?1affff d0000?d7fff sa3011011xxx 64/32 1b0 000?1bffff d8000?dffff sa3111100xxx 64/32 1c0 000?1cffff e0000?e7fff sa3211101xxx 64/32 1d0 000?1dffff e8000?effff sa3311110xxx 64/32 1e0 000?1effff f0000?f7fff sa3411111xxx 64/32 1f0 000?1fffff f8000?fffff
november 27, 2007 s29al016d_00_a7 s29al016d 19 data sheet 7.9 autoselect mode the autoselect mode provides manufa cturer and device identification, an d sector protection verification, through identifier codes output on dq7?dq0. this mo de is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through th e command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 7.4 . in addition, when verifying sector protection, the sector address must appear on the appropr iate highest order address bits (see table 7.2 on page 17 and table 7.3 on page 18 ). table 7.4 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equi pment may then read the corre sponding identifier code on dq7-dq0. to access the autoselect codes in-system, the hos t system can issue the aut oselect command via the command register, as shown in table 10.1 on page 30 . this method does not require v id . see command definitions on page 25 for details on using the autoselect mode. legend l = logic low = v il h = logic high = v ih sa = sector address x = don?t care note the autoselect codes may also be accessed in-system via command sequences. see table 10.1 on page 30 . 7.10 sector protection/unprotection the hardware sector protection feature disables bot h program and erase operations in any sector. the hardware sector unprotection featur e re-enables both program and erase ope rations in previously protected sectors. the device is shipped with all sectors unprotected. sp ansion offers the option of programming and protecting sectors at its factory prior to shipping the device through spansion?s expressflash? service. contact a spansion representative for details. it is possible to determine whether a se ctor is protected or unprotected. see autoselect mode on page 19 for details. sector protection/unprotection can be implemented via two methods. the primary method requires v id on the reset# pin only, and can be im plemented either in-system or via programming equipment. figure 7.2 on page 21 shows the algorithms and figure 17.12 on page 47 shows the timing diagram. this method uses standard micr oprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected pr ior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9 and oe#. this method is compatible with programmer routines wr itten for earlier 3.0 volt-only spansion flash devices. details on this method are provided in a supple ment, publication number 21468. contact a spansion representative to request a copy. table 7.4 s29al016d autoselect codes (high voltage method) description mode ce# oe# we# a19 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 manufacturer id : spansion l l h x x v id xlxlll x 01h device id: s29al016d (top boot block) word l l h xxv id xlxllh 22h c4h byte l l h x c4h device id: s29al016d (bottom boot block) word l l h xxv id xlxllh 22h 49h byte l l h x 49h sector protection verification l l h sa x v id xlxlhl x 01h (protected) x 00h (unprotected)
20 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 7.11 temporary sector unprotect this feature allows temporary unprotection of previo usly protected sectors to change data in-system. the sector unprotect mode is activate d by setting the reset# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the reset# pin, all the prev iously protected sector s are protected again. figure 7.1 shows the algorithm, and figure 17.11 on page 46 shows the timing diagrams, for this feature. figure 7.1 temporary sector unprotect operation notes 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
november 27, 2007 s29al016d_00_a7 s29al016d 21 data sheet figure 7.2 in-system sector protec t/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
22 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 8. common flash memory interface (cfi) the common flash in terface (cfi) specification outlines device and host system software in terrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device -independent, jedec id-independent, and forward- and backward-compatible for the specifie d flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in table 8.1 to table 8.4 on page 23 . in word mode, the upper address bits (a7?msb) must be all zeros. to te rminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in table 8.1 to table 8.4 on page 23 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/overv iew/cfi.html. alternativ ely, contact a spansion representative for copies of these documents. table 8.1 cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) table 8.2 system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0004h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
november 27, 2007 s29al016d_00_a7 s29al016d 23 data sheet table 8.3 device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0015h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0004h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0000h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 0001h 0000h 0020h 0000h erase block region 2 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 001eh 0000h 0000h 0001h erase block region 4 information table 8.4 primary vendor-specif ic extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0030h minor version number, ascii 45h 8ah 0000h address sensitive unlock 0 = required, 1 = not required 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 = 29f040 mode, 02 = 29f016 mode, 03 = 29f400 mode, 04 = 29lv800a mode 4ah 94h 0000h simultaneous operation 00 = not supported, 01 = supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page
24 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 8.1 hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 10.1 on page 30 for command definitions). in addition, the following hardware data protection measures prevent accidental erasure or pr ogramming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down tran sitions, or from system noise. 8.1.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . 8.1.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we # do not initiate a write cycle. 8.1.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 8.1.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is aut omatically reset to reading array data on power-up.
november 27, 2007 s29al016d_00_a7 s29al016d 25 data sheet 9. command definitions writing specific address and data co mmands or sequences into the co mmand register initiates device operations. table 10.1 on page 30 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens fi rst. refer to the appropriate timing diagrams in ac characteristics on page 40 . 9.1 reading array data the device is automatically set to reading array data af ter device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command , the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase- suspended sectors, the device outpu ts status data. after completing a programming operation in the erase suspend mode, the system may once again r ead array data with the same exception. see erase suspend/ erase resume commands on page 28 for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if dq5 goes high, or while in the autoselect mode. see reset command on page 25 . see also requirements for reading array data on page 15 for more information. the read operations on page 40 provides the read parameters, and figure 17.1 on page 40 shows the timing diagram. 9.2 reset command writing the reset command to the device resets the devic e to reading array data. address bits are don?t care for this command. the reset command may be written between the s equence cycles in an erase command sequence before erasing begins. this resets the device to reading a rray data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be writt en between the s equence cycles in a progra m command sequence before programming begins. this resets the device to readi ng array data (also applies to programming in erase suspend mode). once programming begins, however, th e device ignores reset commands until the operation is complete. the reset command may be written between the sequ ence cycles in an autose lect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). 9.3 autoselect command sequence the autoselect command sequence allows the host sys tem to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 10.1 on page 30 shows the address and data requirements. this method is an alternative to that shown in table 7.4 on page 19 , which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselect mo de, and the system may read at any address any number of times, without initia ting another command sequence. a read cycle at address xx00h retrieves the manufactur er code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protect ed, or 00h if it is unprotected. refer to table 7.2 on page 17 and table 7.3 on page 18 for valid sector addresses. the system must write the reset command to exit th e autoselect mode and return to reading array data.
26 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 9.4 word/byte program command sequence the system may program the device by word or byte, depending on the state of the byte# pin. programming is a four-bus-cycle operation. the program command sequen ce is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 10.1 on page 30 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the prog ram operation by using dq7, dq6, or ry/by#. see write operation status on page 31 for information on these status bits. any commands written to the device during the embe dded program algorithm are ignored. note that a hardware reset immediately terminates the programming oper ation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1 . attempting to do so may halt the operation and set dq5 to 1 , or cause the data# polling algorithm to indicate the operation was successful. howe ver, a succeeding read will s how that the data is still 0 . only erase operations can convert a 0 to a 1 . 9.5 unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device fast er than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command , 20h. the device then enters the unl ock bypass mode. a two-cycle unlock bypass progr am command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initia l two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 10.1 on page 30 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. the first cycle must contai n the data 90h; the se cond cycle the data 00h. addresses are don?t care for both cycles. the device then returns to reading array data. figure 9.1 on page 27 illustrates the algorithm fo r the program operation. see erase/program operations on page 43 for parameters, and to figure 17.5 on page 43 for timing diagrams.
november 27, 2007 s29al016d_00_a7 s29al016d 27 data sheet figure 9.1 program operation note see table 10.1 on page 30 for program command sequence. 9.6 chip erase command sequence chip erase is a six bus cycle operatio n. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the emb edded erase algorithm automatically pr eprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings du ring these operations. table 10.1 on page 30 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the em bedded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately te rminates the operation. the chip erase command sequence should be reinitiated once the device has retu rned to reading array data, to ensure data integrity. the system can determine th e status of the erase op eration by using dq7, dq6, dq2, or ry/by#. see write operation status on page 31 for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 9.2 on page 29 illustrates the algorithm fo r the erase operation. see erase/program operations on page 43 for parameters, and figure 17.6 on page 44 for timing diagrams. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
28 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 9.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up co mmand. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 10.1 on page 30 shows the address and data requirements for t he sector erase command sequence. the device does not require the system to preprogram the memo ry prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands ma y be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, ot herwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additi onal sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the de vice to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see dq3: sector erase timer on page 35 .) the time-out begins from the rising ed ge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the sector erase opera tion immediately terminates the operation. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the st atus of the erase operation by using dq7, dq6, dq2, or ry/by#. (refer to write operation status on page 31 for information on these status bits.) figure 9.2 on page 29 illustrates the algorithm for the erase operation. refer to erase/program operations on page 43 for parameters, and to figure 17.6 on page 44 for timing diagrams. 9.8 erase suspend/erase resume commands the erase suspend command allows the system to inte rrupt a sector erase operation and then read data from, or program data to, any sector not selected for er asure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector erase time-out immediatel y terminates the time-out period and suspends the erase operation. addresses are don?t-cares when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediatel y terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device ?erase sus pends? all sectors selected for erasure.) normal read and write timings and command definitions apply. re ading at any address within erase-suspended sectors produces status data on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status on page 31 for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non-suspended sectors. the system can determine the st atus of the program operation using the dq7 or dq6 status bits, just as in t he standard program operation. see write operation status on page 31 for more information.
november 27, 2007 s29al016d_00_a7 s29al016d 29 data sheet the system may also write the autoselect comma nd sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence on page 25 for more information. the system must write the erase resume command (address bits are don?t care ) to exit the erase suspend mode and continue the sector erase operation. furthe r writes of the resume command are ignored. another erase suspend command can be written after the device has resumed erasing. figure 9.2 erase operation notes 1. see table 10.1 on page 30 for erase command sequence. 2. see dq3: sector erase timer on page 35 for more information. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
30 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 10. command definitions legend x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a19?a12 uniquely select any sector. notes 1. see table 7.1 on page 14 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t cares for unlock and command cycles. 5. address bits a19?a11 are don?t cares for unlock and command cycles, unless sa or pa required. 6. no unlock or command cycles required when reading array data. 7. the reset command is required to return to reading array data w hen device is in the autoselect mode, or if dq5 goes high (whi le the device is providing status data). 8. the fourth cycle of the autoselect command sequence is a read cycle. 9. the data is 00h for an unprotected sector and 01h for a prot ected sector. see ?autoselect command sequence? for more informat ion. 10. command is valid when device is ready to read array data or when device is in autoselect mode. 11. the unlock bypass command is required pr ior to the unlock bypass program command. 12. the unlock bypass reset command is required to return to r eading array data when the device is in the unlock bypass mode. f0 is also acceptable. 13. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. table 10.1 s29al016d command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 01 byte aaa 555 aaa device id, top boot block word 4 555 aa 2aa 55 555 90 x01 22c4 byte aaa 555 aaa x02 c4 device id, bottom boot block word 4 555 aa 2aa 55 555 90 x01 2249 byte aaa 555 aaa x02 49 sector protect verify (note 9) word 4 555 aa 2aa 55 555 90 (sa) x02 xx00 xx01 byte aaa 555 aaa (sa) x04 00 01 cfi query (note 10) word 1 55 98 byte aa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30
november 27, 2007 s29al016d_00_a7 s29al016d 31 data sheet 11. write operation status the device provides several bits to determine the stat us of a write operation: dq 2, dq3, dq5, dq6, dq7, and ry/by#. table 11.1 on page 35 and the following subsections describe the functions of these bits. dq7, ry/by#, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. 11.1 dq7: data# polling the data# polling bit, dq7, indicates to the host sys tem whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the embedded program algorithm, the devic e outputs on dq7 the co mplement of the datum programmed to dq7. this dq7 status also appl ies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for appro ximately 1 s, then the device returns to reading array data. during the embedded erase algori thm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete , or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum out put described for the embed ded program algorithm: the erase function changes all the bits in a sector to 1 ; prior to this, the device outputs the complement , or 0 . the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all se ctors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the devic e returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected sectors that are protected. when the system detects dq7 has change d from the complement to true data, it can read valid data at dq7? dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. figure 17.8 on page 45 , illustrates this. table 11.1 on page 35 shows the outputs for data# polling on dq7. figure 11.2 on page 34 shows the data# polling algorithm.
32 s29al016d s29al016d_00_a7 november 27, 2007 data sheet figure 11.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 11.2 ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin th at indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-dra in output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the devic e is actively erasing or programmi ng. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 11.1 on page 35 shows the outputs for ry/by#. figures figure 17.1 on page 40 , figure 17.2 on page 41 , figure 17.5 on page 43 and figure 17.6 on page 44 shows ry/by# for read, reset, program, and erase operations, respectively. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
november 27, 2007 s29al016d_00_a7 s29al016d 33 data sheet 11.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the se ctor erase time-out. during an embedded program or erase algorithm operatio n, successive read cycles to any address cause dq6 to toggle. (the system may use either oe# or ce# to control the read cycles.) when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sect ors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all se lected sectors are protected, the embedded erase algorithm erases the unprotected sect ors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 toget her to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq 6 stops toggling. howe ver, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternativ ely, the system can use dq7 (see dq7: data# polling on page 31 ). if a program address falls within a protected sector, dq6 toggles for approximatel y 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 11.1 on page 35 shows the outputs for toggle bit i on dq6. figure 11.2 on page 34 shows the toggle bit algorithm in flowchart form, and reading toggle bits dq6/dq2 on page 34 explains the algorithm. figure 17.9 on page 45 shows the toggle bit timing diagrams. figure 17.10 on page 46 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii on page 33 . 11.4 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have be en selected for erasure. (the system may use either oe# or ce# to control t he read cycles.) but dq2 cann ot distinguis h whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indica tes whether the device is actively erasing, or is in erase su spend, but cannot distingu ish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 11.1 on page 35 to compare outputs for dq2 and dq6. figure 11.2 on page 34 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 on page 34 explains the algorithm. see also the dq6: toggle bit i on page 33 subsection. figure 17.9 on page 45 shows the toggle bit timing diagram. figure 17.10 on page 46 shows the differences between dq2 and dq6 in graphical form.
34 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 11.5 reading toggle bits dq6/dq2 refer to figure 11.2 on page 34 for the following discussi on. whenever the system in itially begins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the t oggle bit is not toggling, the device has completed the program or erase operati on. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two re ad cycles, the system determi nes that the toggle bit is still to ggling, the system also should note whet her the value of dq5 is high (see the section on dq5) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device di d not complete the operation successful ly, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 11.2 on page 34 ). figure 11.2 toggle bit algorithm notes 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . see text. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 (note 1) (notes 1 , 2 )
november 27, 2007 s29al016d_00_a7 s29al016d 35 data sheet 11.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 . this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure conditi on may appear if the syst em tries to program a 1 to a location that is previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts the operation, and when the operation has exceeded the timing lim its, dq5 produces a 1 . under both these conditions, the system must issue the reset command to re turn the device to reading array data. 11.7 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whet her or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, t he entire time-out also applies after each additional sector erase command. when the time-out is comp lete, dq3 switches from 0 to 1 . the system may ignore dq3 if the system can guarantee that the time between additional sect or erase commands will al ways be less than 50 s. see also sector erase command sequence on page 28 . after the sector erase command sequ ence is written, the system should read the status on dq7 (data# polling) or dq6 (toggle bit i) to ensure the devi ce has accepted the command sequence, and then read dq3. if dq3 is 1 , the internally controlled erase cycle has be gun; all further commands (other than erase suspend) are ignored until the eras e operation is complete. if dq3 is 0 , the device will accept additional sector erase commands. to ensure the command has b een accepted, the system software should check the status of dq3 prior to and following each subsequent se ctor erase command. if dq3 is high on the second status check, the last command might not have been accepted. table 11.1 shows the outputs for dq3. notes 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 35 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. table 11.1 write operation status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
36 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 12. absolute maximum ratings notes 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 36 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 13.2 on page 36 . 2. minimum dc input voltage on pins a9, oe#, and reset# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 on page 36 . maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the devi ce. this is a stress rating only; functional operation of the device at these or any other conditio ns above those indicated in the operational sections of this d ata sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 13. operating ranges industrial (i) devices ambient temperature (t a ) -40c to +85c extended (n) devices ambient temperature (t a ) -40c to +125c v cc supply voltages v cc for standard voltage range 2.7 v to 3.6 v operating ranges define those limits between whic h the functionality of th e device is guaranteed. figure 13.1 maximum negative overshoot waveform figure 13.2 maximum positive overshoot waveform storage temperature plastic packages ?65 c to +150 c ambient temperature with power applied ?65 c to +125 c voltage with respect to ground v cc (note 1) ?0.5 v to +4.0 v a9 , oe# , and reset# (note 2) ?0.5 v to +12.5 v all other pins (note 1) ?0.5 v to v cc +0.5 v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
november 27, 2007 s29al016d_00_a7 s29al016d 37 data sheet 14. dc characteristics 14.1 cmos compatible notes 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . typical v cc is 3.0 v. 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. at extended temperature range (>+85 c), typical current is 5 a and maximum current is 10 a. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 6. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 i cc1 v cc active read current (notes 1 , 2 ) ce# = v il, oe# = v ih, byte mode 10 mhz 15 30 ma 5 mhz 9 16 1 mhz 2 4 ce# = v il, oe# = v ih, word mode 10 mhz 18 35 5 mhz 9 16 1 mhz 2 4 i cc2 v cc active write current (notes 2 , 3 , 5 ) ce# = v il, oe# = v ih 20 35 ma i cc3 v cc standby current (notes 2 , 4 ) ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc standby current during reset (notes 2 , 4 ) reset# = v ss 0.3 v 0.2 a i cc5 automatic sleep mode (notes 2 , 4 , 6 ) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 a v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v oh1 output high voltage i oh = -2.0 ma, v cc = v cc min 2.4 v oh2 i oh = -100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage 2.3 2.5
38 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 14.2 zero power flash figure 14.1 i cc1 current vs. time (showing active and automatic sleep currents) note addresses are switching at 1 mhz figure 14.2 typical i cc1 vs. frequency note t = 25 c 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns 10 8 2 0 1 2345 frequency in mhz supply current in ma 2.7 v 3.6 v 4 6
november 27, 2007 s29al016d_00_a7 s29al016d 39 data sheet 15. test conditions figure 15.1 test setup note diodes are in3064 or equivalent. 16. key to switching waveforms figure 16.1 input waveforms and measurement levels table 15.1 test specifications test condition 70 90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc output timing measurement reference levels 0.5 v cc 2.7 k c l 6.2 k 3.3 v device under te s t waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v cc 0.0 v 0.5 v cc output measurement level input 0.5 v cc
40 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 17. ac characteristics 17.1 read operations notes 1. not 100% tested. 2. see figure 15.1 on page 39 and table 15.1 on page 39 for test specifications. figure 17.1 read operations timings parameter description speed options jedec std test setup 70 90 unit t avav t rc read cycle time (note 1) min 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max 70 90 t elqv t ce chip enable to output delay oe# = v il max 70 90 t glqv t oe output enable to output delay max 30 35 t ehqz t df chip enable to output high z (note 1) max 16 t ghqz t df output enable to output high z (note 1) max 16 t sr/w latency between read and write operations min 20 t oeh output enable hold time (note 1) read min 0 toggle and data# polling min 10 t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t sr/w t oh
november 27, 2007 s29al016d_00_a7 s29al016d 41 data sheet 17.2 hardware reset (reset#) note not 100% tested. figure 17.2 reset# timings 17.3 word/byte configuration (byte#) parameter description all speed options jedec std test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 t rh reset# high time before read (see note) 50 t rpd reset# low to standby mode 20 s t rb ry/by# recovery time 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb parameter speed options jedec std description 70 90 unit t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 16 t fhqv byte# switching high to output active min 70 90
42 s29al016d s29al016d_00_a7 november 27, 2007 data sheet figure 17.3 byte# timings for read operations figure 17.4 byte# timings for write operations note refer to the erase/program operations table for t as and t ah specifications. dq15 output data output (dq0?dq7) ce# oe# byte# t elfl dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t flqz byte# switching from word to byte mode dq15 output data output (dq0?dq7) byte# t elfh dq0?dq14 data output (dq0?dq14) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
november 27, 2007 s29al016d_00_a7 s29al016d 43 data sheet 17.4 erase/program operations notes 1. not 100% tested. 2. see erase and programming performance on page 48 for more information. figure 17.5 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows de vice in word mode. parameter speed options jedec std description 70 90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time 0 t wlax t ah address hold time 45 t dvwh t ds data setup time 35 45 t whdx t dh data hold time 0 t oes output enable setup time 0 t ghwl t ghwl read recovery time before write (oe# high to we# low) 0 t elwl t cs ce# setup time 0 t wheh t ch ce# hold time 0 t wlwh t wp write pulse width 35 t whwl t wph write pulse width high 30 t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte ty p 5 s word 7 t whwh2 t whwh2 sector erase operation (note 2) 0.7 sec t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# 0 ns t busy program/erase valid to ry/by# delay max 90 oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa
44 s29al016d s29al016d_00_a7 november 27, 2007 data sheet figure 17.6 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 31 ). 2. illustration shows de vice in word mode. figure 17.7 back to back read/write cycle timing oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy addresses ce# oe# we# data valid in valid out valid in valid out pa pa pa pa t wc t acc t ce t oe t cp t ah t cph t ghwl t wp t wdh t ds t dh t oh t df t sr/w t rc
november 27, 2007 s29al016d_00_a7 s29al016d 45 data sheet figure 17.8 data# polling timings (during embedded algorithms) note va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read c ycle. figure 17.9 toggle bit timings (during embedded algorithms) note va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va
46 s29al016d s29al016d_00_a7 november 27, 2007 data sheet figure 17.10 dq2 vs. dq6 for erase and erase suspend operations note the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. 17.5 temporary sector unprotect note not 100% tested. figure 17.11 temporary sector unprotect/timing diagram enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence
november 27, 2007 s29al016d_00_a7 s29al016d 47 data sheet figure 17.12 sector protect/unpr otect timing diagram note for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 17.6 alternate ce# controlle d erase/program operations notes 1. not 100% tested. 2. see erase and programming performance on page 48 for more information. sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih parameter speed options jedec std description 70 90 unit t avav t wc write cycle time (note 1) min 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 35 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 35 ns t ehel t cph ce# pulse width high min 30 ns t sr/w latency between read and write operations min 20 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 s word typ 7 t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec
48 s29al016d s29al016d_00_a7 november 27, 2007 data sheet figure 17.13 alternate ce# controlled write operation timings notes 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. 3. word mode address used as an example. 18. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25 c, v cc = 3.0 v, 100,000 cycles, checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7 v, 1,000,000 cycles. 3. the typical chip programming time is consi derably less than the maximum chip programming time listed, since most bytes progra m faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 10.1 on page 30 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 100,000 cycles per sector. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 10 s excludes 00h programming prior to erasure (note 4) chip erase time 25 s byte programming time 7 210 s excludes system level overhead (note 5) word programming time 7 210 s chip programming time (note 3) byte mode 11 33 s word mode 7.2 21.6 s
november 27, 2007 s29al016d_00_a7 s29al016d 49 data sheet 19. tsop, so, and bga pin capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter symbol parameter description test setup package typ max unit c in input capacitance v in = 0 tsop, so 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop, so 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop, so 7.5 9 pf bga 3.9 4.7 pf
50 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 20. physical dimensions 20.1 ts 048?48-pin standard tsop note for reference only. bsc is an ansi standard for basic space centering. 6 2 3 4 5 7 8 9 mo-142 (d) dd 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 8? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 12.00 nom symbol jedec b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for reverse pin out (die up). pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. n +1 2 n 1 2 n 3 reverse pin out (top view) c e a1 a2 2x (n/2 tips) 0.10 9 seating plane a see detail a b b ab e d1 d 2x 2x (n/2 tips) 0.25 2x 0.10 0.10 n 5 +1 n 2 4 5 1 n 2 2 standard pin out (top view) see detail b detail a (c) ? l 0.25mm (0.0098") bsc c r gauge plane parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 0.08mm (0.0031") m c a - b s section b-b detail b x e/2 x = a or b 3355 \ 16-038.10c
november 27, 2007 s29al016d_00_a7 s29al016d 51 data sheet 20.2 vbk048?48-ball fine-pitch ball grid array (fbga) 8.15 mm x 6.15 mm 3338 \ 16-038.25b notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. side view top view seating plane a2 a (4x) 0.10 10 d e c 0.10 a1 c b a c 0.08 bottom view a1 corner b a m 0.15 c m 7 7 6 e se sd 6 5 4 3 2 a b c d e f g 1 h b e1 d1 c 0.08 pin a1 corner index mark package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height a2 0.62 --- 0.76 body thickness d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.35 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
52 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 20.3 so044?44-pin small outline package (sop) 28.20 mm x 13.30 mm dwg rev ac; 10/99
november 27, 2007 s29al016d_00_a7 s29al016d 53 data sheet 21. revision summary 21.1 revision a (may 4, 2004) initial release. 21.2 revision a1 (july 28, 2004) ordering information updated ordering information: model number, speed op tions, and valid combinations for tsop and bga packages. dc characteristics updated max information for i cc2 . physical dimensions updated vbk048 and ts048 drawings. 21.3 revision a2 (december 17, 2004) data sheet type changed from advance information to preliminary. ordering information updated ordering information: small outline package options physical dimensions added so044 package. 21.4 revision a3 (june 1, 2005) global updated status to full data sheet. ordering information added tube and tray packing types. added extended temperature range. valid combinations table added two designators to packing types. added package types for extended temperature. added note for this table. operating ranges added extended temperature range information. erase and programming performance changed byte programing time values for typical and maximum. pin capacitance table added so package to pin capacitance table. global updated trademark.
54 s29al016d s29al016d_00_a7 november 27, 2007 data sheet 21.5 revision a4 (june 17, 2005) ordering information changed packing type from ?1, 3? to ?0, 1, 3? 21.6 revision a5 (may 22, 2006) ac characteristics added t sr/w parameter to read and erase/ program operations tables. a dded back-to-back read/write cycle timing diagram. changed maximum value for t df and t flqz . 21.7 revision a6 (september 7, 2007) command definitions table changed the 2nd cycle data of the unlock by pass reset command from 'f0' to '00'. 21.8 revision a7 (november 27, 2007) figure: read operations timings updated figure
november 27, 2007 s29al016d_00_a7 s29al016d 55 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2007 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse ? , ornand ? , hd-sim ? and combinations thereof, are trademarks of spansion llc in the us and other countries . other names used are for informational purposes only and may be trademarks of their respective owners.

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